(a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for fabricating a metal line in a semiconductor device.
(b) Description of the Related Art
As a semiconductor device becomes more integrated and smaller sized, a gap between lower and upper metal lines is becoming narrower. When the gap between the lower and upper metal lines becomes narrower, a delay of a time constant may increase and thereby an operation speed of the device may decrease. Therefore, for a narrower gap between the lower and upper metal lines, a semiconductor device should be fabricated more precisely.
FIG. 1A to FIG. 1C are sectional views illustrating a conventional process of forming a multiple layer metal line in a semiconductor device.
As shown in FIG. 1A, a lower metal line 12 is formed on a semiconductor substrate 11 having structures of various circuit elements for a semiconductor device thereon and/or therein (e.g., one or more transistors, capacitors, resistors, diodes, etc.), and then a first etch stop layer 13 is formed on the substrate 11 having the lower metal line 12. Subsequently, a first insulating layer 14a, a second etch stop layer 14b, and a second insulating layer 14c are consecutively formed on the first etch stop layer 13 such that an interlayer insulating layer 14 is formed for insulation between metal lines. Then, the first interlayer insulating layer 14 is etched utilizing a dual damascene etching process so as to form a dual damascene pattern 15.
In more detail, the dual damascene pattern 15 is formed as follows. After the first insulating layer 14a and the second etch stop layer 14b are formed on the first etch stop layer 13, the second etch stop layer 14b is partially etched and then the second insulating layer 14c is formed on the second etch stop layer 14b. Subsequently, a trench 15a is formed by partially etching the second insulating layer 14c, and then a via contact hole 15b partially exposing the lower metal line 12 is formed by partially etching the first insulating layer 14a. Thus, the dual damascene pattern 15 is formed to have the trench 15a and the via contact hole 15b. 
As shown in FIG. 1B, a diffusion barrier 16 is formed to cover the semiconductor substrate 11 having the dual damascene pattern 15, and then a copper layer 17 is deposited on the diffusion barrier 16.
When the metal layer 17 is deposited, a top surface of the metal layer 17 undulates due to undulation in an outline of the dual damascene pattern 15 formed on the interlayer insulating layer 14.
For that reason, as a primary planarization process, the top surface of the metal layer 17 is planarized by selectively polishing by a chemical mechanical polishing (CMP) process. That is, the metal layer 17 is polished until the diffusion barrier 16 becomes exposed, and thus the surface of the metal layer 17 becomes more flat.
Subsequently, as shown in FIG. 1C, as a secondary planarization process, another CMP process is performed on the metal layer 17 and the diffusion barrier 16 taking the interlayer insulating layer 14 as an end point, and thereby a metal line is formed in the dual damascene pattern 15. Consequently, an upper metal line 18 is formed in the dual damascene pattern 15 to be connected with the lower metal line 12 through the via contact hole 15b. 
However, according to such a conventional method for forming a metal line in a semiconductor device, the metal line may problematically suffer from a dishing phenomenon that is apt to occur in the trench 15a during the secondary planarization process performed for forming the metal line 18 in the dual damascene pattern 15. Such a dishing phenomenon deteriorates an electrical conductivity of the metal line, and it makes a subsequent process become more difficult.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person or ordinary skill in the art.